1. Field of the Invention
The present invention relates to a driver (source driver) for driving an amplifier circuit and a TFT (Thin Film Transistor) liquid crystal display device applied thereto.
2. Description of Related Art
TFT (Thin Film Transistor) liquid crystal display devices have been widely used. A TFT liquid crystal display device includes a display portion (liquid crystal panel) that contains an LCD (Liquid Crystal Display) module, a gate driver, multiple source drivers, multiple gate lines connected to the gate driver and multiple data lines connected to each of the multiple source drivers. Each of the multiple gate lines is connected to gate electrodes of TFTs in pixels provided in a row. Each of the multiple data lines is connected to drain electrodes of the TFTs in the pixels provided in a column.
The source driver latches multiple display data from outside and performs digital/analog conversion on the multiple display data. Specifically, the source driver selects an output gradation voltage corresponding to the display data from multiple gradation voltages. The source driver includes an output amplifier for outputting the output gradation voltages to the multiple data lines.
The output amplifier includes multiple amplifier circuits. The multiple amplifier circuits have their outputs connected to the multiple data lines, respectively. Moreover, the multiple amplifier circuits operate according to control signals. The multiple amplifier circuits output the output gradation voltages to the multiple data lines according to the control signals, respectively.
In the TFT liquid crystal display device, it is preferable not to operate the multiple amplifier circuits at the same time. If the multiple amplifier circuits operate at the same timing, then a large current flows in a concentrated manner through the source driver. Thus, noise is caused in a power supply line and signal lines in a liquid crystal module. In order to reduce the noise, operation timings of the amplifier circuits need to be shifted from each other.
FIG. 1 shows a configuration of a source driver in a TFT liquid crystal display device described in Patent Document 1. The source driver further includes an amplifier circuit driving portion. The amplifier circuit driving portion includes a control circuit for outputting the control signals described above and delay circuits 141-1 to 141-(N−1) connected in series.
Here, it is assumed that the multiple data lines are N data lines provided from the first to Nth in this order, and that the multiple amplifier circuits are N amplifier circuits provided from the first to Nth in this order. It is also assumed that N is an integer of 4 or more and is a multiple of 2. In Patent Document 1, the N amplifier circuits will be hereinafter referred to as amplifier circuits 136-1 to 136-N, respectively.
An input of the delay circuit 141-1 is connected to the control circuit and the amplifier circuit 136-1. Outputs of the delay circuits 141-1 to 141-(N−1) are connected to the amplifier circuits 136-2 to 136-N, respectively.
FIG. 2 is a timing chart showing an operation of the amplifier circuit driving portion in the source driver shown in FIG. 1.
The control circuit outputs the control signal to the amplifier circuit 136-1. The delay circuits 141-1 to 141-(N−1) delay the control signals by a certain delay time in the order from the second to Nth, and then output the resultant control signals to the amplifier circuits 136-2 to 136-N, respectively.
FIG. 3 shows a configuration of a source driver in a TFT liquid crystal display device described in Patent Document 2. An amplifier circuit driving portion includes a control circuit for outputting the control signals and delay circuits 241-1 to 241-((N/2)−1) connected in parallel.
In Patent Document 2, N amplifier circuits will be hereinafter referred to as amplifier circuits 236-1 to 236-N, respectively.
An input of the delay circuit 241-1 and an input of the delay circuit 241-N are connected to the control circuit and the amplifier circuit 236-1. Outputs of the delay circuits 241-1 to 241-((N/2)−1) are respectively connected to the amplifier circuits 236-2 to 236-(N/2) and also respectively connected to the amplifier circuits 236-(N−1) to 236-((N/2)+1).
FIG. 4 is a timing chart showing an operation of an amplifier circuit driving portion in the source driver shown in FIG. 3.
The control circuit outputs the control signals to the amplifier circuits 236-1 and 236-N.
The delay circuits 241-1 to 241-((N/2)−1) delay the control signals by a certain delay time in the order from the second to (N/2)th, and then output the resultant control signals respectively to the amplifier circuits 136-2 to 136-(N/2) and respectively to the amplifier circuits 36-(N−1) to 36-((N/2)+1).    [Patent Document 1] Japanese Patent Application Laid Open No. 2003-233358    [Patent Document 2] Japanese Patent Application Laid Open No. Hei 7-13509